1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a construction for increasing an operation speed and a degree of integration and facilitating test thereof.
2. Description of the Prior Art
FIG. 28 is a block diagram schematically showing a whole construction of a conventional semiconductor memory device. The construction of the semiconductor memory device shown in FIG. 8 is disclosed, for example, in a paper entitled "1.5V Circuit Technique for 64Mb DRAM", by Nakagome et al, 1990 Symposium on VLSI Circuits, pp. 17 and 18.
Referring to FIG. 28, the conventional semiconductor memory device includes a memory cell array 196 including memory cells arranged in a matrix of rows and columns, a row decoder 199 for selecting a corresponding row in the memory cell array 196 in accordance with an internal row address signal, and a column decoder 192 which generates a column selecting signal for selecting a corresponding column in memory cell array 196 in response to an internal column address signal. Memory cell array 196 includes dynamic memory cells arranged in a matrix of, e.g., 256 rows and 256 columns.
Conventional semiconductor memory device further includes an input/output gate 193 which is responsive to a column selecting signal supplied from the column decoder 192 to connect a corresponding column in memory cell array 196 to internal data transmitting lines IO and /IO, a sense amplifier circuit 194 which detects and amplifies data of memory cells in one row selected by row decoder 199, a precharging circuit 195 for precharging respective columns in memory cell array 196 to a predetermined potential (e.g., a half of the sum of a supply potential Vcc and a ground potential Vss) in a standby state of the semiconductor memory device, an IO (input/output) line precharging circuit 197 for precharging internal data transmitting line pair IO and /IO to a predetermined potential (e.g., "H" level) in a standby state, and an input/output circuit 198 connected to internal data transmitting lines IO and /IO.
Input/output circuit 198 produces internal write data in accordance with an external write data Din and transmits it to internal data transmitting lines IO and /IO in a data writing operation. In a data reading operation, input/output circuit 198 produces an external read data Dout in accordance with internal read data (transmitted from a selected memory cell) on internal data transmitting lines IO and /IO.
In the construction of the semiconductor memory device shown in FIG. 28, a memory cell, which is located at an intersection of the row and column designated by row decoder 199 and column decoder 192, is selected, and the data is written in or read from the selected memory cell.
FIG. 29 shows a construction of a main portion of the semiconductor memory device shown in FIG. 28. In FIG. 29, there is representatively shown a circuit portion related to one column in memory cell array 196. Referring to FIG. 29, memory cell array 196 includes a pair of bit lines BL and /BL providing a column line, and word lines WL1 to WL256 providing row lines each of which is connected to the memory cells in one row. Each memory cell is located at the intersection of each word line and each bit line pair. Specifically, memory cell MC1,1 is located at the intersection of word line WL1 and bit line BL, memory cell MC1,2 is located at the intersection of word line WL2 and complementary bit line /BL, and memory cell MC1,256 is located at the intersection of the word line WL256 and complementary bit line /BL.
Memory cells MC the (reference character "MC" will be used for generically indicating memory cells hereinafter) include dynamic memory cells each of a one-transistor/one-capacitor type. In the dynamic memory cells of the one-transistor/one-capacitor type, capacitors (210, 211 and 212) store information in the form of electrical charges. The information stored in a capacitor is transmitted to a corresponding bit line (BL or /BL) via a transmission gate (207, 208 or 209) in response to a signal WL, which generically indicates a word line selecting signal on the corresponding word line.
Precharging circuit 195 includes precharging transistors 204 and 205 which are responsive to a precharge instructing signal .phi.E to precharge respective bit lines /BL and BL to a predetermined precharge potential VH, and an equalizing transistor 206 which is responsive to precharge instructing signal .phi.E to equalize the potentials of bit lines BL and /BL. Precharging transistors 204 and 205 each are formed of n-channel MOS transistors. Transistor 204 is responsive to precharge instructing signal .phi.E to transmit a precharge potential VH (normally, Vcc/2; Vcc is an operating supply voltage) to complementary bit line /BL. Transistor 205 is responsive to precharge instructing signal .phi.E to transmit precharge potential VH to bit line BL. Equalizing transistor 206 is responsive to precharge instructing signal .phi.E to short-circuit the bit line BL and the complementary bit line /BL.
Sense amplifier circuit 194 includes an N-type sense amplifier NSA which is responsive to an N-type sense amplifier drive signal .phi.N to discharge the potential of the bit line at a lower potential in bit line pair BL and /BL, and a P-type sense amplifier PSA which is responsive to a P-type sense amplifier drive signal .phi.P to charge the potential of the bit line at a higher potential in bit line pair BL and /BL. N-type sense amplifier NSA includes a pair of cross-coupled n-channel MOS transistors 202 and 203. This n-channel MOS transistor 202 has a gate connected to bit line BL, one conduction terminal (drain) connected to complementary bit line /BL and the other conduction terminal (source) for receiving N-type sense amplifier drive signal .phi.N. The n-channel MOS transistor 203 has a gate connected to complementary bit line /BL, one conduction terminal (drain) connected to bit line BL, and the other conduction terminal (source) coupled to receive the N-type sense amplifier drive signal .phi.N.
P-type sense amplifier PSA includes a pair of cross-coupled p-channel MOS transistors 213 and 214. This p-channel MOS transistor 213 has a gate connected to bit line BL, one conduction terminal (drain) connected to complementary bit line /BL, and the other conduction terminal coupled to receive the P-type sense amplifier drive signal .phi.P. The p-channel MOS transistor 214 has a gate connected to complementary bit line /BL, one conduction terminal (drain) connected to bit line BL, and the other conduction terminal coupled to receive the P-type sense amplifier drive signal .phi.P.
Input/output gate 193 includes column selecting gates 201 and 200 which are responsive to a column selecting signal Y1 supplied from the column decoder (see FIG. 27) to connect bit lines BL and /BL to internal data transmitting lines IO and /IO, respectively. Column selecting gates 200 and 201 are formed of n-channel MOS transistors, respectively. Now, operations will be described with reference to an operation timing diagram of FIG. 30.
First, description will be made of a data reading operation in such a case that a selected memory cell MC1, 1 holds the data of "H".
At time t0, a memory cycle starts when precharge instructing signal .phi.E falls to "L". In response to the fall of precharge instructing signal .phi.E, equalizing circuit 195 is inactivated, and bit lines BL and /BL enters a floating state at precharge potential VH.
At time t1, row decoder 199 decodes a received internal row address, and the potential of the corresponding word line WL1 rises to "H". Responsively, transmission gate 208 of memory cell MC1, 1 becomes conductive, so that data of "H" held in the memory capacitor 211 is transmitted to bit line BL. This increases the potential of bit line BL. Since the memory cell does not exist at the intersection of complementary bit line /BL and word line WL1, the potential of complementary bit line /BL remains at precharge potential VH.
At time t2, N-type sense amplifier drive signal .phi.N lowers from an intermediate potential Vcc/2 to "L", and P-type sense amplifier drive signal .phi.P rises from intermediate potential Vcc/2 to "H". Thereby, N-type sense amplifier NSA and P-type sense amplifier PSA are activated, and a potential difference between bit line BL and complementary bit line /BL is differentially amplified. Specifically, the potential of bit line BL changes to "H", and the potential of complementary bit line /BL changes to "L".
At time t3, column decoder 192 generates a column selecting signal Y1 in accordance with a result of decoding of an internal column address, and thus column selecting gates 200 and 201 become conductive. Potentials on bit line BL and complementary bit line /BL are transmitted to internal data transmitting lines IO and /IO. Thereby, the potentials of internal data transmitting lines IO and /IO which have been precharged to a predetermined potentials changed corresponding to those of bit lines BL and /BL. Specifically, the potential of internal data transmitting line IO rises to "H", and the potential of complementary internal data transmitting line /IO slightly lowers.
In the above operation, the potential of complementary internal data transmitting line /IO does not lower to the level of "L", because IO line precharging circuit 197 has pull-up means and the gate transistors 200 and 201 has a relatively large resistance, which suppresses the lowering of the potential. The reason of slight change of the potentials of bit lines BL and /BL at time t3 is that bit lines BL and /BL are connected to internal data transmitting lines IO and /IO precharged to the predetermined precharge potential, and receive the influence of the potential change thereof.
The data read to internal data transmitting lines IO and /IO is detected by an output circuit contained in input/output circuit 198 shown in FIG. 28. This output circuit detects that internal data transmitting line IO has the potential higher than that of internal data transmitting line /IO, and produces external output data Dout of "H".
Then, description will be made of an operation for writing the data of "L" in memory cell MC1,1.
The operation before time t4 is similar to that for reading a data. At time t4, input/output circuit 198 responds to write data Din of "L" to set the potential of internal data transmitting line IO at "L" and set the potential of complementary internal data transmitting line /IO at "H". The data on internal data transmitting lines IO and /IO are transmitted through column selecting gates 201 and 200 to bit lines BL and /BL. Input/output circuit 138 includes an input circuit of which driving ability is larger than latching abilities of sense amplifiers PSA and NSA, and thus bit lines BL and /BL have potentials corresponding to the write data. The data of "L" on bit line BL is transmitted through transmission gate 208 in memory cell MC1,1 to memory cell capacitor 211. Thereby, writing of the data of "L" in memory cell MC1,1 is completed.
At time t5, precharge instructing signal .phi.E is changed to "H". Precharging circuit 195 is activated, and the potentials of bit lines BL and /BL are set at predetermined precharge potential VH for the next memory cycle. Before precharge instructing signal .phi.E rises to "H" at time t5, word line selecting signal WL1 on word line WL1 and column selecting signal Y1 have already lowered to "L" and also sense amplifier drive signals .phi.N and .phi.P have returned to the intermediate potential.
In the semiconductor memory device shown in FIGS. 28 and 29, timing for generating a column selecting signal Y must be as early as possible in order to reduce a time required for reading the data. It is inhibited to generate column selecting signal Y1 before time t2 at which sense amplifiers NSA and PSA are activated, because a slight potential difference generated between bit lines BL and /BL is further reduced due to the connection by the signal Y1 to internal data transmitting lines IO and /IO, and thus sense amplifiers PSA and NSA cannot perform an accurate amplifying operation.
A similar problem is caused in a case that the time t3 at which column selecting signal Y1 is generated is set closer to the time t2 immediately after the generation of sense amplifier drive signals .phi.N and .phi.P. Specifically, if bit lines BL and /BL are connected to internal data transmitting lines IO and /IO before sense amplifiers NSA and PSA sufficiently amplify the potentials of bit lines BL and /BL, the potential difference to be amplified by sense amplifiers NSA and PSA is reduced. Therefore, the sense amplifiers malfunction, and thus cannot accurately amplify the data, resulting in incorrect reading of the data.
Therefore, in the semiconductor memory device shown in FIGS. 28 and 29, it is necessary to generate column selecting signal Y1 in such a state that sense amplifiers NSA and PSA have been activated and the potentials on bit lines BL and /BL have been settled. Therefore, it is impossible to sufficiently reduce an access time in the data reading operation.
In addition, the configuration shown in FIG. 32 does not allow a line test mode operation in which memory cells on a row are simultaneously tested because of the following reason.
In order to carry out the line test mode operation, data of all the memory cells on a row have to be read out simultaneously. If all the bit lines are connected to the internal data transmission lines IO and /IO in order to accomplish the simultaneous reading of data, all the bit lines are interconnected with each other, and a defective memory cell can not be detected because an erroneous data are turned into a correct data by such interconnection. In order to carry out the line test mode operation, a register for storing a test data and a comparator for comparing the test data and a data read out from an associated selected memory cell are required for each respective pair of bit lines. In operation, the output of all the comparators are transferred to a dedicated test data line to be wired-ANDed. Such construction increases the memory cell array area. If a memory device is not provided with the line test mode of operation, memory cells are tested bit by bit, resulting in a long testing time.
FIG. 31 shows another construction of a conventional semiconductor memory device. The semiconductor memory device shown in FIG. 31 is also disclosed, for example, in the previously mentioned paper of 1990 Symposium on VLSI Circuits by Nakagome et al.
Referring to FIG. 31, the semiconductor memory device includes a memory cell array 318 including memory cells arranged in a matrix, a row decoder 319 for selecting a row in memory cell array 318, a column decoder 313 for selecting a column in memory cell array 318, a precharging circuit 317 for precharging each column line in memory cell array 318 to a predetermined potential, and a sense amplifier circuit 316 for detecting and amplifying data of the memory cells in memory cell array 318 selected by row decoder 319, as in the memory device shown in FIG. 28.
The semiconductor memory device shown in FIG. 31 further includes a read gate 315 which transmits a data of a memory cell in the memory cell array 318 selected by the row decoder 319 and column decoder 313 in a data reading operation onto read data transmitting lines O and /O, and a write gate 314 for transmitting a write data to a selected memory cell in memory cell array 318 in the data writing operation. Write gate 314 and read gate 315 are responsive to a column selecting signal from column decoder 313 to connect a corresponding column in memory cell array 318 to internal data transmitting lines I and /I, and O and /O.
For the internal read data transmitting lines O and /O, there are provided an output line precharging circuit 322 for precharging internal read data transmitting lines O and /O to a predetermined potential, and an output circuit 321 for producing an external read data Dout from an internal read data on the internal read data transmitting lines O and /O. For the internal write data transmitting lines I and /I, there is provided an input circuit 320 for transmitting an internal write data to the internal write data transmitting lines I and /I in response to an external write data Din.
The semiconductor memory device shown in FIG. 31 has separated IO structure, in which internal data transmitting lines are separated into the read data transmitting lines O and /O for transmitting read data and the write data transmitting lines I and /I for transmitting write data, and a data reading is carried out before the activation of sense amplifier circuit 316 for reducing an access time in the data reading operation.
FIG. 32 shows a circuit portion related to one column in the semiconductor memory device shown in FIG. 31. Referring to FIG. 32, sense amplifier circuit 316, precharging circuit 317 and memory cell array 318 have the same constructions as sense amplifier circuit 194, precharging circuit 195 and memory cell array 196 shown in FIG. 29, respectively. Only differences therebetween are reference numerals allotted to the respective components and elements, and the constructions of these circuits is not be described in detail.
Read gate 315 includes discharging transistors 224 and 225 which are responsive to the potentials on bit lines /BL1 and BL1 to discharge the potentials of read data transmitting lines O and /O, respectively, and read column selecting gates 222 and 223 which are responsive to a column selecting signal Y1 from column decoder 313 to connect the discharging transistors 224 and 225 to the read data transmitting lines /O and O, respectively. Discharge transistors 224 and 225 include n-channel MOS transistors having gates connected to bit lines /BL1 and BL1, respectively. Each of discharging transistors 224 and 225 has two conduction terminals, one (source) of which is connected to the ground potential.
Read column selecting gates 222 and 223 have gates which receive column selecting signal Y1 for connecting the other conduction terminals (drains) of discharging transistors 224 and 225 to read data transmitting lines /O and O, respectively.
Write gate 314 includes n-channel MOS transistors 220 and 221 which turn on and off in response to a write instructing signal W, and write column selecting gates 218 and 219 which are responsive to column selecting signal Y1 from column decoder 313 to connect the transistors 220 and 221 to the write data transmitting lines /I and I, respectively. Write column selecting gates 218 and 219 are responsive to column selecting signal Y1 to connect the one-conduction terminals of respective transistors 220 and 221 to the read data transmitting line /I and I.
Thus, write gate 314 connects a selected column to write data transmitting lines /I and I only in the data writing operation.
IO line precharging circuit 322 includes pull-up means and precharges the read data transmitting lines O and /O to a predetermined potential ("H" level). Precharging circuit 322 also includes a pull-up stage for pulling up both read data transmitting lines O and /O to "H". Precharging circuit 322 and discharging transistors 244 and 255 form a current-detection type sense circuit for detecting a current. Operations thereof will be described below with reference to an operating waveform diagram of FIG. 33.
In FIG. 33, the following is assumed. Memory cell MC1,1 is selected for writing and reading of data. Memory cell MC1,1 has held data of "H". In the data writing operation, data of "L" is written in memory cell MC1,1.
At time t0, precharge instructing signal .phi.E lowers to "L", and a memory cycle starts. Bit lines BL1 and /BL1 are held in a floating state with precharge potential VH of the intermediate potential. Read data transmitting lines O and /O have been precharged to "H" level.
At time t1, the potential of word line WL1 rises to "H" based on the result of decoding of row decoder 319. Transmission gate 232 of memory cell MC1,1 becomes conductive, and the data of "H" held in memory cell capacitor 235 is transmitted to bit line BL1, so that the potential of bit line BL1 slightly increases. Complementary bit line /BL1 maintains the precharge potential VH.
As the selecting signal WL1 rises, column selecting signal Y1 rises to "H" substantially simultaneously or with a slight delay. A row address signal and a column address signal have been simultaneously applied to the semiconductor memory device in a non-multiplex manner. Row address signal and column address signal, however, may be applied in a time-division multiplexing manner. It is required only to generate column selecting signal Y1 before the activation of sense amplifier circuit 316.
In response to column selecting signal Y1, read column selecting gates 222 and 223 contained in read gate 315 become conductive.
Since the potential of bit line BL1 is higher than that of complementary bit line /BL1, the conductivity of transistor 225 is higher than that of transistor 224, so that the potential of read data transmitting line O is reduced to be lower than the potential of complementary read data transmitting line /O. In this operation, transistor 224 also reduces slightly the potential of complementary read data transmitting line /O.
Output circuit 321 detects the potential difference of read data transmitting lines O and /O to produce a corresponding external output data Dout. Specifically, the output circuit 321 supplies data Dout of "H" when it detects that the potential of internal data transmitting line O is lower than the potential of internal data transmitting line /O.
Then, at time t2, N-type sense amplifier drive signal .phi.N and P-type sense amplifier drive signal .phi.P are changed from the intermediate potential to "L" and "H", respectively, so that N-type sense amplifier NSA and P-type sense amplifier PSA are activated. Thereby, the potential difference between bit line BL and complementary bit line /BL is amplified. In the data reading operation, sense amplifiers NSA and PSA perform the amplifying operation on bit lines BL and /BL, whereby a restoring operation is conducted for restoring the read out data in the selected memory cell MC1,1. This operation completes data reading cycle.
Then, data writing operation will be described. Operations till the activation of sense amplifiers PSA and NSA are identical with those in the data reading process. Input circuit 320 sets the write signal W at "H" at time t3. Before time t3, input circuit 320 also sets the potentials of write data transmitting lines I and /I at levels corresponding to the write data. In this operation, write data transmitting line I is set at "L", and complementary internal write data transmitting line /I is set at "H". In FIG. 33, it is shown that input circuit 320 has set the potential of internal write data transmitting lines I and /I to the levels corresponding to the write data before time t2 at which sense amplifiers PSA and NSA are activated. The timing for generating internal write data by input circuit 320 may be between time t2 and time t3.
At time t3, upon generation of write signal W, transistors 220 and 221 become conductive. Column selecting signal Y1 has already risen to "H". In response to the write data, the potentials of bit lines BL and /BL change to "L" and "H", respectively. The change of signal potentials of bit lines BL and /BL is also transmitted through the read gates formed of transistors 222, 223, 224 and 225 to the read data transmitting lines O and /O, so that the potentials of read data transmitting lines O and /O also change.
The data of "L" on bit line BL is written in memory cell capacitor 235 through transmission gate transistor 232 in memory cell MC1,1.
Then, word line selecting signal WL1 and column selecting signal Y1 are set at an inactive state of "L", and, at time t4, precharge instructing signal .phi.E is set at "H", whereby the data writing cycle is completed. The potentials of bit lines BL and /BL1 return to the intermediate potential VH, and a standby state is set for the next data writing or reading operation.
In the construction shown in FIGS. 31 and 32, the data reading is performed before the time at which sense amplifiers PSA and NSA are driven. In other words, when word line selecting signal WL1 rises to "H", column selecting signal Y1 is set at "H" prior to the activation of sense amplifiers PSA and NSA. Thereby, the data can be read to internal data transmitting lines O and /O before time t2 at the activation of the sense amplifier, so that the time required for reading a data out of a memory cell, i.e., the access time can be reduced.
As described above, in the construction of the semiconductor memory device shown in FIGS. 31 and 32, read data transmitting lines and write data transmitting lines are independently arranged, which enables the data reading at a high speed. In the construction of the semiconductor memory device shown in FIG. 29, the input/output gate are formed of only two transistors, i.e., transistors 200 and 201. In the semiconductor memory device of the separated IO type shown in FIGS. 31 and 32, however, the write gate requires four transistors, i.e., transistors 218, 219, 220 and 221, and the read gate requires four transistors, i.e., transistors 222, 223, 224 and 225. This semiconductor memory device of the separated IO type, therefore, requires totally eight transistors for the read gate and write gate, and thus requires additionally six transistors as compared with the semiconductor memory device in FIG. 29, which disadvantageously increases the chip area.
Further, after the manufacturing, the semiconductor memory devices are subjected to a test for determining whether or not each memory cell can perform a correct operation for storing data. A merged match line test and data line configuration is employed in the construction shown in FIGS. 31 and 32 in order to carry out the line test mode operation. The merged match line test and data line configuration is disclosed in, e.g., "45ns 64Mb DRAM with Merged Match Line Test And Data Line System" by Mori et al., 1991 IEEE, ISSCC, Digest of Technical Papers, pp. 110 and 111.
In this merged match line test and data line configuration, all the column selecting signals are raised to "H" in the test mode. Thereby, all the data of the memory cells connected to a selected one row is simultaneously read onto the read data transmitting lines O and /O. The data on read data transmitting lines 0 and /O is supplied to a test circuit in the test mode. The test circuit detects the potentials of read data transmitting lines O and /O to determine whether or not memory cells in this one row contains a defective memory cell(s). If it does not contain any defective memory cell, the same data has been written in all the memory cells, so that the potentials of read data transmitting lines O and /O change to "H" and "L", respectively. If it contains at least one defective memory cell, both the potentials of read data transmitting lines O and /O change to "L", and the existence of the defective memory cell can be detected.
This simultaneous testing of the memory cells in one row can reduce the test time. In this case, although the test time can be reduced, components in the read gates and the write gates increase in number, resulting in increase of the chip area.